=> R0 = 0 (Read code features)
<= R0 = flags
R1 = pointer to IRQ routine, or zero if not required
This reason is used to determine what is required to run code on the current platform.
StrongARM will return bits 0-4 set.
ARM 6 and 7 with return bits 0-4 clear.
Earlier machines will raise an error.
PlatformFeatures 0 flags
Bit Meaning if set
0 You must tell the OS when a code area changes (OS_SynchroniseCodeAreas)
1 Enabling then disabling interrupts does not allow them a chance to occur
2 Hardware vectors are only readable in 32 bit mode
3 When storing PC, PC+8 is stored (not PC+12)
4 Data aborts occur with 'full early' timing
5 CPU has separate I and D caches
6 Operating system executes in 32 bit mode
7 26 bit mode is not available
8 Processor is M class (supports UMULL etc)
9 Processor supports Thumb mode
10 Processor is E class (supports QADD etc)
11 SWP/SWPB instructions not available
12 Supports LDR/STREX semaphores
13 Supports CLREX plus LDR/STREX[B|H|D] semaphores
14 D cache cannot be safely disabled (OS_MMUControl forbids this)
15 CPU supports extended small page L2 descriptors
16 CPU doesn‘t have a Drain Write Buffer instruction
17 Aborts don‘t correctly follow the documented abort model (e.g. StrongARM pre rev-T; prevents lazy task swapping from being used)
18 CPU is an XScale
19 XScale JTAG is connected
20 High processor vectors are in use (vectors at &FFFF0000 instead of &0)
21-30 Reserved for future expansion
31 OS_PlatformFeatures stack imbalance bug is fixed
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