Register R15 is a special purpose register dedicated to maintaining the ARM's program counter.
In older ARMs which had a 26 bit mode it also had enough spare bits for the status and mode flags, this is no longer the case and the MRS and MSR instructions should be used in preference, along with the separate PSR.
32 bit mode structure:
Bit: 31 27 26 25 2 1 0
R15: ...Program Counter... 0 0
26 bit mode structure (obsolete):
Bit: 31 30 29 28 27 26 25 2 1 0
R15: N Z C V I F ...Program Counter... M1 M0
Where:
N negative flag
Z zero flag
C carry flag
V overflow flag
I interrupts disabled when set
F fast interrupts disabled when set
M1..M0 chosen processor mode (0=user, 1=FIQ, 2=IRQ, 3=supervisor)
Though for LDM and LDR instructions with R15 as the destination, the bottom two bits do become important. bit 0 set causes a jump into Thumb mode and loads with bit 1 set are unpredictable.
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