By separating out the PSR into a register the program counter is freed from the 64Mbyte limitations imposed by running in the obsolete 26 bit mode.
PSR structure:
Bit: 31 30 29 28 27 25 8 7 6 5 4 3 2 1 0
R15: N Z C V Q ...Reserved... I F T M4 M3 M2 M1 M0
Where:
N negative flag
Z zero flag
C carry flag
V overflow flag
Q overflow/saturation of DSP instruction (E variant ARMs only)
I interrupts disabled when set
F fast interrupts disabled when set
T running in thumb mode
M4 running in 32 bit mode
M3..M0 chosen processor mode
(0=user, 1=FIQ, 2=IRQ, 3=supervisor,
7=abort, 11=undefined, 15=system)
Note that only 14 of the potential 32 mode combinations are currently valid.
There are infact two PSRs, the current PSR (CPSR) and the saved PSR (SPSR) - be careful when using MRS and MSR that you are dealing with the correct one: the saved PSR is used as a copy of the CPSR when an exception occurs.
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